060351152JAT2A [KYOCERA AVX]
Ceramic Capacitor, Multilayer, Ceramic, 100V, 5% +Tol, 5% -Tol, X7R, 15% TC, 0.0015uF, Surface Mount, 0603, CHIP;
| 型号： | 060351152JAT2A |
| 厂家： | 
KYOCERA AVX |
| 描述： | Ceramic Capacitor, Multilayer, Ceramic, 100V, 5% +Tol, 5% -Tol, X7R, 15% TC, 0.0015uF, Surface Mount, 0603, CHIP 电容器 |
| 文件： | 总18页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X7R Dielectric
General Specifications
X7R formulations are called “temperature stable” ceramics
and fall into EIA Class II materials. X7R is the most popular
of these intermediate dielectric constant materials. Its tem-
perature variation of capacitance is within ±15% from
-55°C to +125°C. This capacitance change is non-linear.
Capacitance for X7R varies under the influence of electrical
operating conditions such as voltage and frequency.
X7R dielectric chip usage covers the broad spectrum of
industrial applications where known changes in capaci-
tance due to applied voltages are acceptable.
PART NUMBER (see page 2 for complete part number explanation)
0805
5
C
103
M
A
T
2
A
Size
(L" x W")
Voltage
4V = 4
Dielectric
X7R = C
Capacitance Capacitance
Failure
Rate
A = Not
Applicable
Terminations
T = Plated Ni
and Sn
Packaging
2 = 7" Reel
4 = 13" Reel
7 = Bulk Cass.
9 = Bulk
Special
Code
A = Std.
Product
Code (In pF)
2 Sig. Digits +
Number of
Zeros
Tolerance
J = ± 5%
6.3V = 6
10V = Z
16V = Y
25V = 3
50V = 5
100V = 1
200V = 2
500V = 7
K = ±10%
M = ± 20%
7 = Gold
Plated
Contact
Factory For
Multiples
X7R Dielectric
Insulation Resistance vs Temperature
ꢀ Capacitance vs. Frequency
Typical Temperature Coefficient
10,000
1,000
100
+30
+20
+10
10
5
0
-5
0
-10
-20
-30
-10
-15
-20
-25
0
0
20
40
60
80
100
120
-60 -40
100 140
120
1KHz
10 KHz
100 KHz
1 MHz
10 MHz
-20
0
20 40 60 80
Frequency
Temperature °C
Temperature °C
Variation of Impedance with Cap Value
Impedance vs. Frequency
1,000 pF vs. 10,000 pF - X7R
0805
Variation of Impedance with Chip Size
Impedance vs. Frequency
100,000 pF - X7R
Variation of Impedance with Chip Size
Impedance vs. Frequency
10,000 pF - X7R
10
10.00
10
1206
0805
1210
1206
0805
1210
1,000 pF
10,000 pF
1.0
0.1
.01
1.00
1.0
0.10
0.01
0.1
.01
100
1,000
1
10
100
1000
10
100
1,000
1
10
Frequency, MHz
Frequency, MHz
Frequency, MHz
12
X7R Dielectric
Specifications and Test Methods
Parameter/Test
Operating Temperature Range
Capacitance
X7R Specification Limits
Measuring Conditions
Temperature Cycle Chamber
-55ºC to +125ºC
Within specified tolerance
≤ 2.5% for ≥ 50V DC rating
≤ 3.0% for 25V DC rating
≤ 3.5% for 16V DC rating
≤ 5.0% for ≤ 10V DC rating
100,000MΩ or 1000MΩ - µF,
whichever is less
Freq.: 1.0 kHz ± 10%
Voltage: 1.0Vrms ± .2V
For Cap > 10 µF, 0.5Vrms @ 120Hz
Dissipation Factor
Charge device with rated voltage for
120 ± 5 secs @ room temp/humidity
Charge device with 300% of rated voltage for
1-5 seconds, w/charge and discharge current
limited to 50 mA (max)
Insulation Resistance
Dielectric Strength
No breakdown or visual defects
Appearance
Capacitance
Variation
Dissipation
Factor
No defects
Deflection: 2mm
Test Time: 30 seconds
≤ ±12%
Resistance to
Flexure
1mm/sec
Meets Initial Values (As Above)
Stresses
Insulation
Resistance
≥ Initial Value x 0.3
90 mm
≥ 95% of each terminal should be covered
with fresh solder
Dip device in eutectic solder at 230 ± 5ºC
for 5.0 ± 0.5 seconds
Solderability
Appearance
Capacitance
Variation
Dissipation
Factor
Insulation
Resistance
Dielectric
Strength
Appearance
Capacitance
Variation
No defects, <25% leaching of either end terminal
≤ ±7.5%
Dip device in eutectic solder at 260ºC for 60
seconds. Store at room temperature for 24 ± 2
hours before measuring electrical properties.
Resistance to
Solder Heat
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Meets Initial Values (As Above)
No visual defects
Step 1: -55ºC ± 2º
Step 2: Room Temp
30 ± 3 minutes
≤ ±7.5%
≤ 3 minutes
Dissipation
Factor
Insulation
Resistance
Dielectric
Strength
Appearance
Capacitance
Variation
Dissipation
Factor
Insulation
Resistance
Dielectric
Strength
Appearance
Capacitance
Variation
Dissipation
Factor
Insulation
Resistance
Dielectric
Strength
Thermal
Shock
Meets Initial Values (As Above)
Meets Initial Values (As Above)
Step 3: +125ºC ± 2º
Step 4: Room Temp
30 ± 3 minutes
≤ 3 minutes
Repeat for 5 cycles and measure after
24 ± 2 hours at room temperature
Meets Initial Values (As Above)
No visual defects
Charge device with twice rated voltage in
test chamber set at 125ºC ± 2ºC
for 1000 hours (+48, -0)
≤ ±12.5%
≤ Initial Value x 2.0 (See Above)
≥ Initial Value x 0.3 (See Above)
Load Life
Remove from test chamber and stabilize
at room temperature for 24 ± 2 hours
before measuring.
Meets Initial Values (As Above)
No visual defects
Store in a test chamber set at 85ºC ± 2ºC/
85% ± 5% relative humidity for 1000 hours
(+48, -0) with rated voltage applied.
≤ ±12.5%
Load
Humidity
≤ Initial Value x 2.0 (See Above)
≥ Initial Value x 0.3 (See Above)
Meets Initial Values (As Above)
Remove from chamber and stabilize at
room temperature and humidity for
24 ± 2 hours before measuring.
13
X7R Dielectric
Capacitance Range
PREFERRED SIZES ARE SHADED
SIZE
0201
0402
0603
0805
1206
Soldering
Packaging
Reflow Only
All Paper
Reflow Only
All Paper
Reflow Only
All Paper
Reflow/Wave
Paper/Embossed
Reflow/Wave
Paper/Embossed
MM
(in.)
0.60 ± 0.03
(0.024 ± 0.001)
1.00 ± 0.10
(0.040 ± 0.004)
1.60 ± 0.15
(0.063 ± 0.006)
2.01 ± 0.20
(0.079 ± 0.008)
3.20 ± 0.20
(0.126 ± 0.008)
(L) Length
MM
(in.)
0.30 ± 0.03
(0.011 ± 0.001)
0.50 ± 0.10
(0.020 ± 0.004)
0.81 ± 0.15
(0.032 ± 0.006)
1.25 ± 0.20
(0.049 ± 0.008)
1.60 ± 0.20
(0.063 ± 0.008)
(W) Width
MM
(in.)
MM
(in.)
0.30 ± 0.03
(0.011 ± 0.001)
0.15 ± 0.05
(0.006 ± 0.002)
0.06
(0.024)
0.25 ± 0.15
(0.010 ± 0.006)
0.09
(0.035)
0.35 ± 0.15
(0.014 ± 0.006)
1.30
(0.051)
0.50 ± 0.25
(0.020 ± 0.010)
1.50
(0.059)
0.50 ± 0.25
(0.020 ± 0.010)
(T) Max Thickness
(t) Terminal
WVDC
100
150
220
330
470
16
A
A
A
A
A
A
A
16
25
50
10
16
25
50
100
10
16
25
50
100
200
10
16
25
50
100
200
500
Cap
(pF)
C
C
C
C
C
C
C
C
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
M
J
J
J
J
J
J
J
J
J
K
K
K
K
M
M
M
M
P
680
1000
1500
2200
3300
4700
6800
0.010
0.015
0.022
0.033
0.047
0.068
0.10
0.15
0.22
0.33
0.47
0.68
1.0
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
M
M
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
M
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
J
J
J
J
J
J
J
J
J
J
J
J
J
J
C
C
C
C
C
C
C
Cap
(µF
J
J
M
J
P
G
G
G
G
M
M
M
M
P
G
G
G
J
J
M
G
G
G
G
J
J
M
M
M
N
N
N
M
M
M
P
Q
Q
W
L
1.5
2.2
3.3
ꢀ
T
ꢀ
4.7
10
t
22
47
100
WVDC
16
16
25
50
10
16
25
50
100
10
16
25
50
100
200
10
16
25
50
100
200
500
SIZE
0201
0402
0603
0805
1206
Letter
Max.
Thickness
A
C
0.56
(0.022)
E
0.71
(0.028)
G
0.86
(0.034)
J
K
1.02
(0.040)
M
1.27
(0.050)
N
1.40
(0.055)
P
1.52
(0.060)
Q
1.78
(0.070)
X
2.29
(0.090)
Y
Z
2.79
(0.110)
0.33
(0.013)
0.94
(0.037)
2.54
(0.100)
PAPER
EMBOSSED
14
X7R Dielectric
Capacitance Range
PREFERRED SIZES ARE SHADED
SIZE
1210
1812
1825
2220
2225
Soldering
Reflow Only
Reflow Only
Reflow Only
Reflow Only
Reflow Only
Packaging
Paper/Embossed
3.20 ± 0.20
(0.126 ± 0.008)
All Embossed
4.50 ± 0.30
(0.177 ± 0.012)
All Embossed
4.50 ± 0.30
(0.177 ± 0.012)
All Embossed
5.70 ± 0.40
(0.225 ± 0.016)
All Embossed
5.72 ± 0.25
(0.225 ± 0.010)
MM
(in.)
(L) Length
MM
(in.)
2.50 ± 0.20
(0.098 ± 0.008)
3.20 ± 0.20
(0.126 ± 0.008)
6.40 ± 0.40
(0.252 ± 0.016)
5.00 ± 0.40
(0.197 ± 0.016)
6.35 ± 0.25
(0.250 ± 0.010)
(W) Width
MM
(in.)
MM
(in.)
1.70
(0.067)
0.50 ± 0.25
(0.020 ± 0.010)
1.70
(0.067)
0.61 ± 0.36
(0.024 ± 0.014)
1.70
(0.067)
0.61 ± 0.36
(0.024 ± 0.014)
2.30
(0.090)
0.64 ± 0.39
(0.025 ± 0.015)
1.70
(0.067)
0.64 ± 0.39
(0.025 ± 0.015)
(T) Max Thickness
(t) Terminal
WVDC
100
150
220
330
470
10
16
25
50
100
200
500
50
100
200
500
50
100
6.3
50
100
200
50
100
Cap
(pF)
W
L
ꢀ
T
ꢀ
680
1000
1500
2200
3300
4700
6800
0.010
0.015
0.022
0.033
0.047
0.068
0.10
0.15
0.22
0.33
0.47
0.68
1.0
t
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
M
N
N
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
M
N
N
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
P
P
J
J
J
J
J
J
J
J
J
J
J
J
J
J
J
M
X
X
J
J
J
J
J
J
J
J
J
J
J
J
M
P
Z
Z
Z
Z
J
J
J
J
J
J
J
J
J
M
M
M
M
M
M
P
Cap
(µF
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
M
P
K
K
K
K
K
K
K
P
K
P
P
X
Z
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Z
X
X
X
X
X
X
X
X
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
P
P
P
P
P
P
P
P
P
P
P
P
P
Q
J
M
M
P
Q
X
1.5
2.2
X
X
Z
3.3
4.7
10
Q
Z
Z
22
47
100
WVDC
10
16
25
50
100
200
500
50
100
200
500
50
100
6.3
50
100
200
50
100
SIZE
Letter
1210
1812
1825
P
2220
2225
A
C
E
G
J
K
M
N
Q
X
Y
Z
Max.
Thickness
0.33
(0.013)
0.56
(0.022)
0.71
(0.028)
0.86
(0.034)
0.94
(0.037)
1.02
(0.040)
1.27
(0.050)
1.40
(0.055)
1.52
(0.060)
1.78
(0.070)
2.29
(0.090)
2.54
(0.100)
2.79
(0.110)
PAPER
EMBOSSED
15
Packaging of Chip Components
Automatic Insertion Packaging
TAPE & REEL QUANTITIES
All tape and reel specifications are in compliance with RS481.
8mm
12mm
Paper or Embossed Carrier
Embossed Only
0612, 0508, 0805, 1206,
1210
1812, 1825
2220, 2225
1808
Paper Only
0201, 0306, 0402, 0603
Qty. per Reel/7" Reel
2,000, 3,000 or 4,000, 10,000, 15,000
Contact factory for exact quantity
3,000
500, 1,000
Contact factory for exact quantity
Qty. per Reel/13" Reel
5,000, 10,000, 50,000
10,000
4,000
Contact factory for exact quantity
REEL DIMENSIONS
Tape
A
Max.
B*
Min.
D*
Min.
N
Min.
W2
Max.
C
W1
W3
Size(1)
7.90 Min.
(0.311)
+1.5
14.4
8.40 -0.0
8mm
(0.331 -+00..0059
)
)
(0.567)
10.9 Max.
(0.429)
330
(12.992)
1.5
(0.059)
13.0 -+00..2500
20.2
(0.795)
50.0
(1.969)
(0.512 +-00..000280
)
11.9 Min.
(0.469)
15.4 Max.
(0.607)
+2.0
18.4
(0.724)
12.4 -0.0
12mm
(0.488 +-00..0079
Metric dimensions will govern.
English measurements rounded and for reference only.
(1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision.
60
Embossed Carrier Configuration
8 & 12mm Tape Only
10 PITCHES CUMULATIVE
TOLERANCE ON TAPE
0.2mm ( 0.008)
EMBOSSMENT
P0
T2
T
D0
P2
DEFORMATION
BETWEEN
EMBOSSMENTS
Chip Orientation
E1
A0
W
F
E2
TOP COVER
TAPE
B1
B0
P1
K0
T1
D1 FOR COMPONENTS
2.00 mm x 1.20 mm AND
LARGER (0.079 x 0.047)
CENTER LINES
OF CAVITY
S1
MAX. CAVITY
SIZE - SEE NOTE 1
B1 IS FOR TAPE READER REFERENCE ONLY
INCLUDING DRAFT CONCENTRIC AROUND B0
User Direction of Feed
8 & 12mm Embossed Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size
D0
E
P0
P2
S1 Min.
T Max.
T1
+0.10
8mm
and
12mm
1.50 -0.0
1.75 ± 0.10
4.0 ± 0.10
2.0 ± 0.05
0.60
(0.024)
0.60
(0.024)
0.10
(0.004)
Max.
(0.059 +-00..0004
)
(0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002)
VARIABLE DIMENSIONS
Tape Size
B1
Max.
D1
Min.
E2
Min.
F
P1
R
T2
W
Max.
A0 B0 K0
Min.
See Note 5 See Note 2
4.35
(0.171)
1.00
6.25
3.50 ± 0.05
4.00 ± 0.10
25.0
(0.984)
2.50 Max.
(0.098)
8.30
(0.327)
8mm
See Note 1
See Note 1
See Note 1
See Note 1
(0.039) (0.246) (0.138 ± 0.002) (0.157 ± 0.004)
8.20
(0.323)
1.50
10.25
5.50 ± 0.05
4.00 ± 0.10
30.0
(1.181)
6.50 Max.
(0.256)
12.3
(0.484)
12mm
(0.059) (0.404) (0.217 ± 0.002) (0.157 ± 0.004)
8mm
1/2 Pitch
4.35
(0.171)
1.00
6.25
3.50 ± 0.05
2.00 ± 0.10
25.0
(0.984)
2.50 Max.
(0.098)
8.30
(0.327)
(0.039) (0.246) (0.138 ± 0.002) (0.079 ± 0.004)
12mm
Double
Pitch
8.20
(0.323)
1.50
10.25
5.50 ± 0.05
8.00 ± 0.10
30.0
(1.181)
6.50 Max.
(0.256)
12.3
(0.484)
(0.059) (0.404) (0.217 ± 0.002) (0.315 ± 0.004)
NOTES:
2. Tape with or without components shall pass around radius “R” without damage.
1. The cavity defined by A , B0, and K shall be configured to provide the following:
Surround the component with sufficient clearance such that:
0
0
3. Bar code labeling (if required) shall be on the side of the reel opposite the round sprocket holes.
Refer to EIA-556.
a) the component does not protrude beyond the sealing plane of the cover tape.
b) the component can be removed from the cavity in a vertical direction without mechanical
restriction, after the cover tape has been removed.
4. B1 dimension is a reference dimension for tape feeder clearance only.
5. If P1 = 2.0mm, the tape may not properly index in all tape feeders.
c) rotation of the component is limited to 20º maximum (see Sketches D & E).
d) lateral movement of the component is restricted to 0.5mm maximum (see Sketch F).
Top View, Sketch "F"
Component Lateral Movements
0.50mm (0.020)
Maximum
0.50mm (0.020)
Maximum
61
Paper Carrier Configuration
8 & 12mm Tape Only
10 PITCHES CUMULATIVE
TOLERANCE ON TAPE
0.20mm ( 0.008)
P0
D0
P2
T
E1
BOTTOM
COVER
TAPE
TOP
COVER
TAPE
F
W
E2
B0
G
T1
A0
P1
CAVITY SIZE
SEE NOTE 1
T1
CENTER LINES
OF CAVITY
User Direction of Feed
8 & 12mm Paper Tape
Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size
D0
E
P0
P2
T1
G. Min.
R Min.
+0.10
1.50 -0.0
8mm
and
12mm
1.75 ± 0.10
4.00 ± 0.10
2.00 ± 0.05
0.10
(0.004)
Max.
0.75
(0.030)
Min.
25.0 (0.984)
See Note 2
Min.
(0.059 -+00..0004
)
(0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002)
VARIABLE DIMENSIONS
P1
Tape Size
E2 Min.
F
W
A0 B0
See Note 1
T
See Note 4
+0.30
8mm
4.00 ± 0.10
(0.157 ± 0.004)
6.25
(0.246)
3.50 ± 0.05
(0.138 ± 0.002)
8.00 -0.10
(0.315 +-00..000142
)
1.10mm
(0.043) Max.
for Paper Base
Tape and
4.00 ± 0.010
(0.157 ± 0.004)
10.25
(0.404)
5.50 ± 0.05
(0.217 ± 0.002) (0.472 ± 0.012)
12.0 ± 0.30
12mm
1.60mm
(0.063) Max.
for Non-Paper
Base Compositions
+0.30
8mm
1/2 Pitch
2.00 ± 0.05
(0.079 ± 0.002)
6.25
(0.246)
3.50 ± 0.05
(0.138 ± 0.002)
8.00 -0.10
(0.315 +-00..000142
)
12mm
Double
Pitch
8.00 ± 0.10
(0.315 ± 0.004)
10.25
(0.404)
5.50 ± 0.05
(0.217 ± 0.002) (0.472 ± 0.012)
12.0 ± 0.30
NOTES:
2. Tape with or without components shall pass around radius “R” without damage.
1. The cavity defined by A , B0, and T shall be configured to provide sufficient clearance
surrounding the component so that:
0
3. Bar code labeling (if required) shall be on the side of the reel opposite the sprocket
holes. Refer to EIA-556.
a) the component does not protrude beyond either surface of the carrier tape;
b) the component can be removed from the cavity in a vertical direction without
mechanical restriction after the top cover tape has been removed;
c) rotation of the component is limited to 20º maximum (see Sketches A & B);
d) lateral movement of the component is restricted to 0.5mm maximum
(see Sketch C).
4. If P1 = 2.0mm, the tape may not properly index in all tape feeders.
Top View, Sketch "C"
Component Lateral
0.50mm (0.020)
Maximum
0.50mm (0.020)
Maximum
Bar Code Labeling Standard
AVX bar code labeling is available and follows latest version of EIA-556
62
Bulk Case Packaging
BENEFITS
BULK FEEDER
• Easier handling
• Smaller packaging volume
(1/20 of T/R packaging)
• Easier inventory control
• Flexibility
Case
Cassette
• Recyclable
Gate
Shooter
CASE DIMENSIONS
Shutter
Slider
12mm
36mm
Mounter
Head
Expanded Drawing
110mm
Chips
Attachment Base
CASE QUANTITIES
Part Size
0402
0603
0805
1206
Qty.
(pcs / cassette)
10,000 (T=.023")
8,000 (T=.031")
6,000 (T=.043")
5,000 (T=.023")
4,000 (T=.032")
3,000 (T=.044")
80,000
15,000
63
Basic Capacitor Formulas
I. Capacitance (farads)
XI. Equivalent Series Resistance (ohms)
.224 K A
E.S.R. = (D.F.) (Xc) = (D.F.) / (2 π fC)
English: C =
TD
XII. Power Loss (watts)
.0884 K A
2
Metric: C =
Power Loss = (2 π fCV ) (D.F.)
TD
XIII. KVA (Kilowatts)
II. Energy stored in capacitors (J oules, watt - sec)
-3
2
KVA = 2 π fCV x 10
2
1
E = ⁄ CV
2
XIV. Temperature Characteristic (ppm/°C)
III. Linear charge of a capacitor (Amperes)
Ct – C25
dV
T.C. =
x 106
I = C
C25 (Tt – 25)
dt
XV. Cap Drift (% )
C1 – C2
C1
IV. Total Impedance of a capacitor (ohms)
2
2
Z = ꢀ
C.D. =
x 100
RS + (X - X )
C
L
V. Capacitive Reactance (ohms)
XVI. Reliability of Ceramic Capacitors
1
x =
c
L0
V
X
Tt
To
Y
t
=
2 π fC
(V ) ( )
L
o
t
VI. Inductive Reactance (ohms)
XVII. Capacitors in Series (current the same)
xL = 2 π fL
Any Number:
1
C
1
1
C2
1
---
=
+
VII. Phase Angles:
C1
C
N
T
Ideal Capacitors: Current leads voltage 90°
Ideal Inductors: Current lags voltage 90°
Ideal Resistors: Current in phase with voltage
C1 C2
C1 + C2
Two: C
=
T
XVIII. Capacitors in Parallel (voltage the same)
= C1 + C2 --- + C
VIII. Dissipation Factor (% )
C
T
N
E.S.R.
D.F.= tan ꢀ (loss angle) =
= (2 πfC) (E.S.R.)
X
XIX. Aging Rate
c
IX. Power Factor (% )
A.R. = %D C/decade of time
P.F. = Sine ꢀ (loss angle) = Cos (phase angle)
P.F. = (when less than 10%) = DF
f
XX. Decibels
V
1
db = 20 log
X. Quality Factor (dimensionless)
V
2
1
D.F.
Q = Cotan ꢀ (loss angle) =
METRIC PREFIXES
SYMBOLS
X 10-12
X 10-9
X 10-6
X 10-3
X 10-1
X 10+1
X 10+3
X 10+6
X 10+9
X 10+12
t
K
A
TD
V
t
= Dielectric Constant
f
= frequency
= Inductance
= Loss angle
= Phase angle
L
= Test life
Pico
Nano
Micro
Milli
= Area
L
ꢀ
V
= Test voltage
t
= Dielectric thickness
= Voltage
V
= Operating voltage
= Test temperature
= Operating temperature
o
Deci
Deca
Kilo
T
t
f
Mega
Giga
Tera
= time
X & Y = exponent effect of voltage and temp.
To
R
s
= Series Resistance
Lo
= Operating life
64
General Description
Basic Construction – A multilayer ceramic (MLC) capaci-
tor is a monolithic block of ceramic containing two sets of
offset, interleaved planar electrodes that extend to two
opposite surfaces of the ceramic dielectric. This simple
structure requires a considerable amount of sophistication,
both in material and manufacture, to produce it in the quality
and quantities needed in today’s electronic equipment.
Electrode
Ceramic Layer
End Terminations
Terminated
Edge
Terminated
Edge
Margin
Electrodes
Multilayer Ceramic Capacitor
Figure 1
Formulations – Multilayer ceramic capacitors are available
in both Class 1 and Class 2 formulations. Temperature
compensating formulation are Class 1 and temperature
stable and general application formulations are classified
as Class 2.
Class 2 – EIA Class 2 capacitors typically are based on the
chemistry of barium titanate and provide a wide range of
capacitance values and temperature stability. The most
commonly used Class 2 dielectrics are X7R and Y5V. The
X7R provides intermediate capacitance values which vary
only ±15% over the temperature range of -55°C to 125°C. It
finds applications where stability over a wide temperature
range is required.
Class 1 – Class 1 capacitors or temperature compensating
capacitors are usually made from mixtures of titanates
where barium titanate is normally not a major part of the
mix. They have predictable temperature coefficients and
in general, do not have an aging characteristic. Thus they
are the most stable capacitor available. The most popular
Class 1 multilayer ceramic capacitors are C0G (NP0)
temperature compensating capacitors (negative-positive
0 ppm/°C).
The Y5V provides the highest capacitance values and is
used in applications where limited temperature changes are
expected. The capacitance value for Y5V can vary from
22% to -82% over the -30°C to 85°C temperature range.
All Class 2 capacitors vary in capacitance value under the
influence of temperature, operating voltage (both AC and
DC), and frequency. For additional information on perfor-
mance changes with operating conditions, consult AVX’s
software, SpiCap.
65
General Description
Effects of Voltage – Variations in voltage have little effect
on Class 1 dielectric but does affect the capacitance and
dissipation factor of Class 2 dielectrics. The application of
DC voltage reduces both the capacitance and dissipation
factor while the application of an AC voltage within a
reasonable range tends to increase both capacitance and
dissipation factor readings. If a high enough AC voltage is
applied, eventually it will reduce capacitance just as a DC
voltage will. Figure 2 shows the effects of AC voltage.
Table 1: EIA and MIL Temperature Stable and General
Application Codes
EIA CODE
Percent Capacity Change Over Temperature Range
RS198
Temperature Range
X7
X6
X5
Y5
Z5
-55°C to +125°C
-55°C to +105°C
-55°C to +85°C
-30°C to +85°C
+10°C to +85°C
Cap. Change vs. A.C. Volts
X7R
Code
Percent Capacity Change
50
40
30
20
D
E
F
P
R
S
±3.3%
±4.7%
±7.5%
±10%
±15%
±22%
10
0
T
U
V
+22% , -33%
+22% , - 56%
+22% , -82%
12.5
25
37.5
50
EXAMPLE – A capacitor is desired with the capacitance value at 25°C
to increase no more than 7.5% or decrease no more than 7.5% from
-30°C to +85°C. EIA Code will be Y5F.
Volts AC at 1.0 KHz
Figure 2
Capacitor specifications specify the AC voltage at which to
measure (normally 0.5 or 1 VAC) and application of the
wrong voltage can cause spurious readings. Figure 3 gives
the voltage coefficient of dissipation factor for various AC
voltages at 1 kilohertz. Applications of different frequencies
will affect the percentage changes versus voltages.
MIL CODE
Symbol
Temperature Range
A
B
C
-55°C to +85°C
-55°C to +125°C
-55°C to +150°C
D.F. vs. A.C. Measurement Volts
X7R
Cap. Change
Zero Volts
Cap. Change
Rated Volts
Symbol
10.0
Curve 1 - 100 VDC Rated Capacitor
Curve 2 - 50 VDC Rated Capacitor
Curve 3 - 25 VDC Rated Capacitor
Curve 3
Curve 2
R
S
W
X
Y
Z
+15% , -15%
+22% , -22%
+22% , -56%
+15% , -15%
+30% , -70%
+20% , -20%
+15% , -40%
+22% , -56%
+22% , -66%
+15% , -25%
+30% , -80%
+20% , -30%
8.0
6.0
4.0
Curve 1
2.0
0
Temperature characteris tic is s pecified by combining range and
change symbols, for example BR or AW. Specification slash sheets
indicate the characteristic applicable to a given style of capacitor.
.5
1.0
1.5
2.0
2.5
AC Measurement Volts at 1.0 KHz
In specifying capacitance change with temperature for Class
2 materials, EIA expresses the capacitance change over an
operating temperature range by a 3 symbol code. The first
symbol represents the cold temperature end of the temper-
ature range, the second represents the upper limit of the
operating temperature range and the third symbol repre-
s e nts the c a p a c ita nc e c ha nge a llowe d ove r the
operating temperature range. Table 1 provides a detailed
explanation of the EIA system.
Figure 3
Typical effect of the application of DC voltage is shown in
Figure 4. The voltage coefficient is more pronounced for
higher K dielectrics. These figures are shown for room tem-
perature conditions. The combination characteristic known
as voltage temperature limits which shows the effects of
rated voltage over the operating temperature range is
shown in Figure 5 for the military BX characteristic.
66
General Description
tends to de-age capacitors and is why re-reading of capaci-
tance after 12 or 24 hours is allowed in military specifica-
tions after dielectric strength tests have been performed.
Typical Cap. Change vs. D.C. Volts
X7R
2.5
0
Typical Curve of Aging Rate
X7R
+1.5
0
-2.5
-5
-7.5
-10
-1.5
25%
50%
75%
100%
-3.0
-4.5
Percent Rated Volts
Figure 4
Typical Cap. Change vs. Temperature
X7R
-6.0
-7.5
+20
+10
0
1
10
100 1000 10,000 100,000
Hours
0VDC
Characteristic Max. Aging Rate %/Decade
None
2
7
C0G (NP0)
X7R, X5R
Y5V
-10
-20
-30
Figure 6
Effe c ts of Fre que nc y – Frequency affects capacitance
and impedance characteristics of capacitors. This effect is
much more pronounced in high dielectric constant ceramic
formulation than in low K formulations. AVX’s SpiCap soft-
ware generates impedance, ESR, series inductance, series
resonant frequency and capacitance all as functions of
frequency, temperature and DC bias for standard chip sizes
and styles. It is available free from AVX and can be down-
loaded for free from AVX website: www.avx.com.
-55 -35 -15 +5 +25 +45 +65 +85 +105 +125
Temperature Degrees Centigrade
Figure 5
Effe c ts of Tim e – Class 2 ceramic capacitors change
capacitance and dissipation factor with time as well as tem-
perature, voltage and frequency. This change with time is
known as aging. Aging is caused by a gradual re-alignment
of the crystalline structure of the ceramic and produces an
exponential loss in capacitance and decrease in dissipation
factor versus time. A typical curve of aging rate for semi-
stable ceramics is shown in Figure 6.
If a Class 2 ceramic capacitor that has been sitting on the
shelf for a period of time, is heated above its curie point,
1
(125°C for 4 hours or 150°C for ⁄
2
hour will suffice) the part
will de-age and return to its initial capacitance and dissi-
pation factor readings. Because the capacitance changes
rapidly, immediately after de-aging, the basic capacitance
measurements are normally referred to a time period some-
time after the de-aging process. Various manufacturers use
different time bases but the most popular one is one day
or twenty-four hours after “last heat.” Change in the aging
curve can be caused by the application of voltage and
other stresses. The possible changes in capacitance due to
de-aging by heating the unit explain why capacitance
changes are allowed after test, such as temperature cycling,
moisture resistance, etc., in MIL specs. The application of
high voltages such as dielectric withstanding voltages also
67
General Description
Effe c ts o f Me c ha nic a l Stre s s – High “K” dielectric
ceramic capacitors exhibit some low level piezoelectric
reactions under mechanical stress. As a general statement,
the piezoelectric output is higher, the higher the dielectric
constant of the ceramic. It is desirable to investigate this
effect before using high “K” dielectrics as coupling capaci-
tors in extremely low level applications.
Energy Stored – The energy which can be stored in a
capacitor is given by the formula:
2
E = 1⁄
2
CV
E = energy in joules (watts-sec)
V = applied voltage
C = capacitance in farads
Reliability – Historically ceramic capacitors have been one
of the most reliable types of capacitors in use today.
The approximate formula for the reliability of a ceramic
capacitor is:
Potential Change – A capacitor is a reactive component
which reacts against a change in potential across it. This is
shown by the equation for the linear charge of a capacitor:
Lo
Lt
V
X
Tt
Y
t
=
ꢁ ꢁ
ꢁV ꢁ
T
o
o
dV
dt
Iideal
=
C
where
Lo = operating life
Lt = test life
Tt = test temperature and
To = operating temperature
in °C
where
I = Current
C = Capacitance
V = test voltage
t
Vo = operating voltage
X,Y = see text
dV/dt = Slope of voltage transition across capacitor
Thus an infinite current would be required to instantly
change the potential across a capacitor. The amount of
current a capacitor can “sink” is determined by the above
equation.
Historically for ceramic capacitors exponent X has been
considered as 3. The exponent Y for temperature effects
typically tends to run about 8.
Equivalent Circuit – A capacitor, as a practical device,
exhibits not only capacitance but also resistance and
inductance. A simplified schematic for the equivalent circuit
is:
A capacitor is a component which is capable of storing
electrical energy. It consists of two conductive plates (elec-
trodes) separated by insulating material which is called the
dielectric. A typical formula for determining capacitance is:
C = Capacitance
L = Inductance
Rs = Series Resistance
Rp = Parallel Resistance
.224 KA
C =
t
R P
C = capacitance (picofarads)
K = dielectric constant (Vacuum = 1)
A = area in square inches
t = separation between the plates in inches
(thickness of dielectric)
L
R S
.224 = conversion constant
C
(.0884 for metric system in cm)
Reactance – Since the insulation resistance (Rp) is normal-
Capacitance – The standard unit of capacitance is the
farad. A capacitor has a capacitance of 1 farad when 1
coulomb charges it to 1 volt. One farad is a very large unit
and most capacitors have values in the micro (10-6), nano
(10-9) or pico (10-12) farad level.
ly very high, the total impedance of a capacitor is:
2
Z = R2S + (X - X )
C
L
ꢀ
where
Z = Total Impedance
Dielectric Constant – In the formula for capacitance given
above the dielectric constant of a vacuum is arbitrarily cho-
sen as the number 1. Dielectric constants of other materials
are then compared to the dielectric constant of a vacuum.
Rs = Series Resistance
XC = Capacitive Reactance =
1
2 π fC
XL = Inductive Reactance = 2 π fL
Dielectric Thickness – Capacitance is indirectly propor-
tional to the separation between electrodes. Lower voltage
requirements mean thinner dielectrics and greater capaci-
tance per volume.
The variation of a capacitor’s impedance with frequency
determines its effectiveness in many applications.
Phas e Angle – Power Factor and Dissipation Factor are
often confused since they are both measures of the loss in
a capacitor under AC application and are often almost
identical in value. In a “perfect” capacitor the current in the
capacitor will lead the voltage by 90°.
Area – Capacitance is directly proportional to the area of
the electrodes. Since the other variables in the equation are
usually set by the performance desired, area is the easiest
parameter to modify to obtain a specific capacitance within
a material group.
68
General Description
di
dt
The
seen in current microprocessors can be as high as
I (Ideal)
0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic
inductance can cause a voltage spike of 30mV. While this
does not sound very drastic, with the Vcc for microproces-
sors decreasing at the current rate, this can be a fairly large
percentage.
I (Actual)
Loss
Angle
Phase
Angle
ꢀ
Another important, often overlooked, reason for knowing
the parasitic inductance is the calculation of the resonant
frequency. This can be important for high frequency, by-
pass capacitors, as the resonant point will give the most
signal attenuation. The resonant frequency is calculated
from the simple equation:
f
V
IRs
In practice the current leads the voltage by some other
phase angle due to the series resistance RS. The comple-
ment of this angle is called the loss angle and:
fres =
1
2ꢁꢀLC
Ins ula tio n Re s is ta nc e – Insulation Resistance is the
resistance measured across the terminals of a capacitor
and consists principally of the parallel resistance RP shown
in the equivalent circuit. As capacitance values and hence
the area of dielectric increases, the I.R. decreases and
hence the product (C x IR or RC) is often specified in ohm
faradsor more commonly megohm-microfarads. Leakage
current is determined by dividing the rated voltage by IR
(Ohm’s Law).
Power Factor (P.F.) = Cos f or Sine ꢀ
Dissipation Factor (D.F.) = tan ꢀ
for small values of ꢀ the tan and sine are essentially equal
which has led to the common interchangeability of the two
terms in the industry.
Eq uiva le nt Se rie s Re s is ta nc e – The term E.S.R. or
Equivalent Series Resistance combines all losses both
series and parallel in a capacitor at a given frequency so
that the equivalent circuit is reduced to a simple R-C series
connection.
Dielectric Strength – Dielectric Strength is an expression
of the ability of a material to withstand an electrical stress.
Although dielectric strength is ordinarily expressed in volts, it
is actually dependent on the thickness of the dielectric and
thus is also more generically a function of volts/mil.
Dielectric Abs orption – A capacitor does not discharge
instantaneously upon application of a short circuit, but
drains gradually after the capacitance proper has been dis-
charged. It is common practice to measure the dielectric
absorption by determining the “reappearing voltage” which
appears across a capacitor at some point in time after it has
been fully discharged under short circuit conditions.
E.S.R.
C
Dissipation Factor – The DF/PF of a capacitor tells what
percent of the apparent power input will turn to heat in the
capacitor.
Corona – Corona is the ionization of air or other vapors
which causes them to conduct current. It is especially
prevalent in high voltage units but can occur with low voltages
as well where high voltage gradients occur. The energy
discharged degrades the performance of the capacitor and
can in time cause catastrophic failures.
E.S.R.
XC
Dissipation Factor =
= (2 π fC) (E.S.R.)
The watts loss are:
2
Watts loss = (2 π fCV ) (D.F.)
Very low values of dissipation factor are expressed as their
reciprocal for convenience. These are called the “Q” or
Quality factor of capacitors.
Parasitic Inductance – The parasitic inductance of capac-
itors is becoming more and more important in the decou-
pling of today’s high speed digital systems. The relationship
between the inductance and the ripple voltage induced on
the DC voltage line can be seen from the simple inductance
equation:
di
dt
V = L
69
Surface Mounting Guide
MLC Chip Capacitors
REFLOW SOLDERING
Case Size
0402
D1
D2
D3
D4
D5
D2
1.70 (0.07)
2.30 (0.09)
3.00 (0.12)
4.00 (0.16)
4.00 (0.16)
5.60 (0.22)
5.60 (0.22)
5.60 (0.22)
6.60 (0.26)
6.60 (0.26)
0.60 (0.02)
0.80 (0.03)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04))
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
0.50 (0.02)
0.70 (0.03)
1.00 (0.04)
2.00 (0.09)
2.00 (0.09)
3.60 (0.14)
3.60 (0.14)
3.60 (0.14)
4.60 (0.18)
4.60 (0.18)
0.60 (0.02)
0.80 (0.03)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
1.00 (0.04)
0.50 (0.02)
0.75 (0.03)
1.25 (0.05)
1.60 (0.06)
2.50 (0.10)
2.00 (0.08)
3.00 (0.12)
6.35 (0.25)
5.00 (0.20)
6.35 (0.25)
0603
0805
1206
1210
1808
1812
1825
2220
D1
D3
D4
D5
2225
Dimensions in millimeters (inches)
Component Pad Design
Component pads should be designed to achieve good
solder filets and minimize component movement during
reflow soldering. Pad designs are given below for the most
common sizes of multilayer ceramic capacitors for both
wave and reflow soldering. The basis of these designs is:
• Pad width equal to component width. It is permissible to
decrease this to as low as 85% of component width but it
is not advisable to go below this.
• Pad overlap 0.5mm beneath component.
• Pad extension 0.5mm beyond components for reflow and
1.0mm for wave soldering.
WAVE SOLDERING
D2
Case Size
0603
D1
D2
D3
D4
D5
D1
D3
D4
3.10 (0.12)
4.00 (0.15)
5.00 (0.19)
1.20 (0.05)
1.50 (0.06)
1.50 (0.06)
0.70 (0.03)
1.00 (0.04)
2.00 (0.09)
1.20 (0.05)
1.50 (0.06)
1.50 (0.06)
0.75 (0.03)
1.25 (0.05)
1.60 (0.06)
0805
1206
Dimensions in millimeters (inches)
D5
Component Spacing
Preheat & Soldering
For wave soldering components, must be spaced sufficiently
far apart to avoid bridging or shadowing (inability of solder
to penetrate properly into small spaces). This is less impor-
tant for reflow soldering but sufficient space must be
allowed to enable rework should it be required.
The rate of preheat should not exceed 4°C/second to
prevent thermal shock. A better maximum figure is about
2°C/second.
For capacitors size 1206 and below, with a maximum
thickness of 1.25mm, it is generally permissible to allow a
temperature differential from preheat to soldering of 150°C.
In all other cases this differential should not exceed 100°C.
For further specific application or process advice, please
consult AVX.
Cleaning
≥1.5mm (0.06)
≥1mm (0.04)
Care should be taken to ensure that the capacitors are
thoroughly cleaned of flux residues especially the space
beneath the capacitor. Such residues may otherwise
become conductive and effectively offer a low resistance
bypass to the capacitor.
≥1mm (0.04)
Ultrasonic cleaning is permissible, the recommended
conditions being 8 Watts/litre at 20-45 kHz, with a process
cycle of 2 minutes vapor rinse, 2 minutes immersion in the
ultrasonic solvent bath and finally 2 minutes vapor rinse.
70
Surface Mounting Guide
MLC Chip Capacitors
Wave
APPLICATION NOTES
300
Storage
Preheat
Natural
Cooling
Good solderability is maintained for at least twelve months,
provided the components are stored in their “as received”
packaging at less than 40°C and 70% RH.
250
200
150
100
50
T
Solderability
230°C
to
Terminations to be well soldered after immersion in a 60/40
tin/lead solder bath at 235 ± 5°C for 2 ± 1 seconds.
250°C
Leaching
Terminations will resist leaching for at least the immersion
times and conditions shown below.
Solder
Tin/Lead/Silver Temp. °C
60/40/0 260 ± 5
Solder
Immersion Time
Seconds
0
Termination Type
1 to 2 min
3 sec. max
Nickel Barrier
30 ± 1
(Preheat chips before soldering)
T/maximum 150°C
Recommended Soldering Profiles
Lead-Free Wave Soldering
The recommended peak temperature for lead-free wave
soldering is 250°C-260°C for 3-5 seconds. The other para-
meters of the profile remains the same as above.
Reflow
300
Natural
Cooling
Preheat
The following should be noted by customers changing from
lead based systems to the new lead free pastes.
250
200
a) The visual standards used for evaluation of solder joints
will need to be modified as lead free joints are not as
bright as with tin-lead pastes and the fillet may not be as
large.
220°C
to
250°C
150
100
50
b) Resin color may darken slightly due to the increase in
temperature required for the new pastes.
c) Lead-free solder pastes do not allow the same self align-
ment as lead containing systems. Standard mounting
pads are acceptable, but machine set up may need to be
modified.
0
1min
(Minimize soldering time)
10 sec. max
1min
General
Surface mounting chip multilayer ceramic capacitors
are designed for soldering to printed circuit boards or other
substrates. The construction of the components is such that
they will withstand the time/temperature profiles used in both
wave and reflow soldering methods.
Lead-Free Reflow Profile
300
250
200
150
100
Handling
Chip multilayer ceramic capacitors should be handled with
care to avoid damage or contamination from perspiration
and skin oils. The use of tweezers or vacuum pick ups
is strongly recommended for individual components. Bulk
handling should ensure that abrasion and mechanical shock
are minimized. Taped and reeled components provides the
ideal medium for direct presentation to the placement
machine. Any mechanical shock should be minimized during
handling chip multilayer ceramic capacitors.
50
0
0
50
100
150
200
250
300
Time (s)
• Pre-heating: 150°C 15°C / 60-90s
• Max. Peak Gradient 2.5°C/s
• Peak Temperature: 245°C 5°C
• Time at >230°C: 40s Max.
Preheat
It is important to avoid the possibility of thermal shock during
soldering and carefully controlled preheat is therefore
required. The rate of preheat should not exceed 4°C/second
71
Surface Mounting Guide
MLC Chip Capacitors
and a target figure 2°C/second is recommended. Although
an 80°C to 120°C temperature differential is preferred,
recent developments allow a temperature differential
between the component surface and the soldering temper-
ature of 150°C (Maximum) for capacitors of 1210 size and
below with a maximum thickness of 1.25mm. The user is
cautioned that the risk of thermal shock increases as chip
size or temperature differential increases.
POST SOLDER HANDLING
Once SMP components are soldered to the board, any
bending or flexure of the PCB applies stresses to the sol-
dered joints of the components. For leaded devices, the
stresses are absorbed by the compliancy of the metal leads
and generally don’t result in problems unless the stress is
large enough to fracture the soldered connection.
Ceramic capacitors are more susceptible to such stress
because they don’t have compliant leads and are brittle in
nature. The most frequent failure mode is low DC resistance
or short circuit. The second failure mode is significant loss
of capacitance due to severing of contact between sets of
the internal electrodes.
Soldering
Mildly activated rosin fluxes are preferred. The minimum
amount of solder to give a good joint should be used.
Excessive solder can lead to damage from the stresses
caus ed by the difference in coefficients of expans ion
between solder, chip and substrate. AVX terminations are
suitable for all wave and reflow soldering systems. If hand
soldering cannot be avoided, the preferred technique is the
utilization of hot air soldering tools.
Cracks caused by mechanical flexure are very easily identi-
fied and generally take one of the following two general
forms:
Cooling
Natural cooling in air is preferred, as this minimizes stresses
within the soldered joint. When forced air cooling is used,
cooling rate should not exceed 4°C/second. Quenching
is not recommended but if used, maximum temperature
differentials should be observed according to the preheat
conditions above.
Cleaning
Type A:
Flux residues may be hygroscopic or acidic and must be
removed. AVX MLC capacitors are acceptable for use with
all of the solvents described in the specifications MIL-STD-
202 and EIA-RS-198. Alcohol based solvents are acceptable
and properly controlled water cleaning systems are also
acceptable. Many other solvents have been proven successful,
and most solvents that are acceptable to other components
on circuit assemblies are equally acceptable for use with
ceramic capacitors.
Angled crack between bottom of device to top of solder joint.
Type B:
Fracture from top of device to bottom of device.
Mechanical cracks are often hidden underneath the termi-
nation and are difficult to see externally. However, if one end
termination falls off during the removal process from PCB,
this is one indication that the cause of failure was excessive
mechanical stress due to board warping.
72
Surface Mounting Guide
MLC Chip Capacitors
COMMON CAUSES OF
REWORKING OF MLCs
MECHANICAL CRACKING
Thermal shock is common in MLCs that are manually
attached or reworked with a soldering iron. AVX strongly
recommends that any reworking of MLCs be done with hot
air reflow rather than soldering irons. It is practically impossi-
ble to cause any thermal shock in ceramic capacitors when
using hot air reflow.
The most common source for mechanical stress is board
depanelization equipment, such as manual breakapart, v-
cutters and shear presses. Improperly aligned or dull cutters
may cause torqueing of the PCB resulting in flex stresses
being transmitted to components near the board edge.
Another common source of flexural stress is contact during
parametric testing when test points are probed. If the PCB
is allowed to flex during the test cycle, nearby ceramic
capacitors may be broken.
However direct contact by the soldering iron tip often caus-
es thermal cracks that may fail at a later date. If rework by
soldering iron is absolutely necessary, it is recommended
that the wattage of the iron be less than 30 watts and the
tip temperature be <300ºC. Rework should be performed
by applying the solder iron tip to the pad and not directly
contacting any part of the ceramic capacitor.
A third common source is board to board connections at
vertical connectors where cables or other PCBs are con-
nected to the PCB. If the board is not supported during the
plug/unplug cycle, it may flex and cause damage to nearby
components.
Special care should also be taken when handling large (>6"
on a side) PCBs since they more easily flex or warp than
smaller boards.
Solder Tip
Solder Tip
Preferred Method - No Direct Part Contact
Poor Method - Direct Contact with Part
PCB BOARD DESIGN
To avoid many of the handling problems, AVX recommends that MLCs be located at least .2" away from nearest edge of
board. However when this is not possible, AVX recommends that the panel be routed along the cut line, adjacent to where the
MLC is located.
No Stress Relief for MLCs
Routed Cut Line Relieves Stress on MLC
73
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